System-on-a-chip (SoC) integrated circuits which include digital, analog, power management or radio frequency (RF) circuit elements have been popular for mobile devices and other electronic devices that have stringent form factor requirements. More recently, three-dimensional integrated circuits (3D ICs) with multiple tiers of dies for placement of circuit elements are being designed for SoC implementations with further reduced chip footprints to allow mobile and other electronic devices to achieve even smaller form factors. In mobile applications and various other applications, it is also often desirable to operate such 3D IC chips with low power consumption which may be achievable by low-power circuit design. In theory, low-power design may be realized by lowering the dynamic power, that is, C·V2·f, where C is the capacitance, V is the voltage, and f is the frequency, as well as the static leakage power, that is, Ileak·Vdd, where Ileak is the leakage current and Vdd is the power supply voltage. The dynamic power and the static leakage power may be reduced by reducing the power supply voltage Vdd. However, reducing the power supply voltage Vdd results in reduced clock speed and degraded performance.
Various IC design techniques have been devised in attempts to improve the performance of low-power integrated circuits. Such design techniques include, for example, voltage boosting, deep pipeline, multiple threshold voltages (multi-Vt), and hardware parallelism. However, these design techniques often trade performance with other important metrics such as power and area footprint. For example, raising the power supply voltage Vdd results in an increase in dynamic and leakage power but would contradict the principle of low-power circuit design. Moreover, in advanced technology nodes such as 22 nm or 14 nm nodes, for example, a high power supply voltage Vdd is generally not available. Furthermore, many modern integrated circuits typically have large resistance-capacitance (RC) loads and generally do not respond well to voltage increases.
Deep pipelining by reducing the logic depth of the pipeline stage is often costly. Performance of circuits designed by using the deep pipelining technique may be hampered by sensitivity to clock skew at high frequencies and insertion delay at critical paths, in addition to power and area penalties due to the insertion of extra flops. Although the multi-Vt technique may alleviate some critical path issues, it may, however, result in increased technological complexity and fabrication cost. Hardware parallelism, on the other hand, may present considerable challenges in instruction coding due to the limit of Amdahl's Law and may incur area penalties.